1. Field of the Invention
The present invention relates to a low voltage triggered electrostatic discharge (ESD) protection device and its applications. In particular, the present invention relates to a modified lateral silicon controlled rectifier especially suited to the process of shallow trench isolation (STI).
2. Description of the Related Art
As the semiconductor manufacturing process develops, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as semiconductor process advances into the deep sub-micron stage, scaled-down devices and thinner gate oxides are more vulnerable in terms of ESD stress. Thus, the input/output ports on IC chips are usually designed to include ESD protect devices or circuits for protecting the devices in IC chips from ESD damage.
FIG. 1 shows a cross-section view of a conventional Low-Voltage-Triggered lateral Semiconductor Control Rectifier (LVTSCR), triggered by an NMOS. The LVTSCR in FIG. 1 is constructed by a lateral SCR (LSCR) composed of P+ region 14, N well 10, P substrate 12 and N+ region 16, and an NMOS composed of a gate 20, a drain of N+ region 18 and a source of N+ region 16. In FIG. 1, P+ region 14 and N+ region 16 are respectively used the anode and the cathode of the LVTSCR. NMOS is used to lower the trigger voltage of the LSCR, such that the combined device is named LVTSCR. While an LVTSCR is implemented by a process flow with a conventional field oxide process, the doped regions in the surface of the substrate are isolated from each other by field oxide layers 26. The arrow and the dash line in FIG. 1 illustrates the ESD current path while the LVTSCR is triggered to release ESD stress. When positive ESD stress pulses on the anode of the LVTSCR in FIG. 1 and the cathode is relatively coupled to ground, the ESD current conducts from P+ region 14 (anode), detours under the field oxide 26, reaches N+ region 16, and is released to the coupled ground.
However, semiconductor process progress has begun to replace the field oxide layers in ICs with shallow trench isolation (STI) regions. FIG. 2 is a cross-section view of the LVTSCR in FIG. 1 wherein the field oxide layers 26 in FIG. 1 are replaced by STI regions 30. One of the strongest advantages of employing the STI process in an IC is that the substrate surface of the IC will become more even, and the subsequent electric connections are more easily fabricated on the substrate surface. To perform electrical isolation between devices, however, STI regions require a certain depth, usually deeper than that of a diffusion region, as shown in FIG. 2. When a positive ESD stress pulses on the anode of the LVTSCR in FIG. 2 and the cathode is relatively coupled to ground, the ESD current conducts from P+ region 14 (anode), detours under the STI region 30, reaches N+ region 16, and is released to the coupled ground. The ESD current path in FIG. 2, in comparison with that in FIG. 1, is distinctly longer due to the increased depth of the STI region 30.
Therefore, it is more difficult for the ESD current path in FIG. 2 to release ESD stress than in FIG. 1, such that the LVTSCR in FIG. 2 has a longer turn-on time and a lower ESD tolerance. Thus, replacing field-oxide structure with STI structure may degrade the ESD tolerance of an ESD protection device.
An object of the present invention is to provide an ESD protection device having a quick turn-on speed and superior ESD tolerance even though the ESD protection device is fabricated with the STI process.
Another object of the present invention is to provide ESD protection circuits employing the ESD protection device of the present invention.
As mentioned above, the ESD protection device of the present invention comprises a first well of a first conductive type, a second well of a second conductive type, a MOS of the first conductive type, a first doped region of the second conductive type, a second doped region of the first conductive type and a dummy gate. The second conductive type is opposite to the first conductive type. The second well contacts the first well to form a junction. The MOS comprises a control gate, a first drain/source region of the first conductive type and a second drain/source region of the first conductive type. The control gate is positioned on the second well. The first drain/source region is formed on the junction. The second drain/source region is formed on the second well and coupled to a first pad. The first doped region is coupled to a second pad and formed on the first well. The first doped region associates with the first well, the second well and the second drain/source region to construct a lateral semiconductor controlled rectifier (LSCR). The second doped region is formed on the surface of the well and between the first doped region and the first drain/source region. The dummy gate is positioned between the first drain/source region and the second doped region and on the first well.
The LSCR has an anode and a cathode respectively coupled to a first pad and a second pad.
The ESD protection device of the present invention has the advantage of quicker turn-on speed and higher ESD tolerance, in comparison with the prior art, since no STI structure stands between the anode and the cathode to lengthen the ESD current path.